In general, in a nonvolatile memory device, a memory cell is comprised of a transistor having a gate comprised of a floating gate and a control gate, a source and a drain. The sources of the respective cells are typically connected in a line. A method of forming memory devices having source regions connected in a line is disclosed in U.S. Pat. No. 5,120,671, entitled "Process for Self Aligning a Source Region with a Field Oxide Region and a Polysilicon Gate." In particular, U.S. Pat. No. 5,120,671 discloses a method for forming a source region self-aligned to a field oxide isolation region and a polysilicon word line. However, according to this method, a cell gate being on an active region and a source region in an active region may be damaged during steps for forming a source line by etching a field oxide layer and performing an ion implantation step. This will be explained with reference to FIGS. 1A through 2B. Here, FIGS. 1A and 2A show a field oxide isolation region, and FIGS. 1B and 2B show an active region.
FIGS. 1A and 1B show a process of etching a field oxide layer, in which a field oxide layer 33 is partially exposed (the hatched portion of 33) using polysilicon word lines and gates 9 and 11 formed on a semiconductor substrate 29, and masks 41, and then etched. The gates 9 and 11 and the semiconductor substrate 29 in the active region as well as the field oxide layer 33 are partially exposed by the masks 41 for forming a source line, as shown in FIG. 1B. In a state where the gates 9 and 11 and the semiconductor substrate 29 in the active region are exposed, if the field oxide layer 33 is etched, the surfaces of the gates 9 and 11 and the surface of the semiconductor substrate 29 may be partially etched as well. Thus, the thicknesses of the gates may be reduced, which increases the gate resistance. Also, crystalline defects may be generated in the semiconductor substrate, and such defects may degrade the current-voltage characteristics of the device formed therein.
FIGS. 2A and 2B show source ion implantation steps, in which impurity ions are implanted into the semiconductor substrate 29 exposed by the etched field oxide layer 17 and 19. At this time, as shown in FIG. 2B, since parts of the gates 9 and 11 formed on the active region are subjected to the ion implantation process, the gates 9 and 11 may be physically damaged. As a result, electrical damage such as charge accumulation or an increased local electric field may be generated and cause malfunction of the device during operation.